1. Field of the Invention
The invention relates to a combined logic signals generator. The generator enables all or a certain number of combinations of p logic signals at a level 1 and of N-p logic signals at a level 0 to be formed amongst the N outputs (QP1, QP2 . . . QPN) which the generator comprises (N and p are constant).
The generator is applied, for example, to the study of the consequences of the failure of components used in the safety systems of nuclear power stations by producing, in association with a logic simulator, the combinations of the failures of the various components; in this application, where the object is to describe the combinations of failing components which would cause the failure of a global system, each component of the system is simulated by logic gates, each of the gates being connected to one of the outputs QP1 . . . QPN. In dependence on the state of the means Pi, the corresponding gate simulates the passing or non-passing state (satisfactory state or failure) of the component of the system. For each of the combinations generated on the means P, the response of the simulator is analysed to find out whether it is a combination causing the failure of the global system or not. The list of these combinations is a result which then enables the global system to be analysed for dependability studies.
Clearly, however, the generator can be applied to the simulation of all the logic systems operating from the reception of logic signals of levels 0 or 1 received at their inputs. Clearly also the generator can supply combinations of p logic signals at a level 0 and N-p logic signals of level 1 amongst the N outputs which the generator comprises.
2. Description of the Prior Art
A system is known which allows the rotation, amongst the N outputs which it comprises, of all combinations of p outputs on which logic signals of level 1 are available, with the remaining N-p outputs supplying logic signals of level 0. That system comprises a binary counter of N outputs on which a sweeping is carried out of all the possible combinations of such outputs or of a certain number of such combinations; however, except for low values of N, the total number of combinations to be swept is generally very large. Moreover, the combinations, having only P logic levels 1, are worked out amongst other combinations which do not correspond to that number p of levels 1. For reasons of time and expense, all that can be done is to sweep the first combinations one by one, two by two, and p by p, on the counter outputs. Generally such combinations are obtained only from slow systems limited to low values of p, the systems being piloted by computers.
In the case of reliability studies of logic systems, the object is to find the list of failing elements which cause the total failure of the system. In the present state of the art, therefore, the simulation of logic systems is a complicated, lengthy and expensive operation.
The known system described hereinbefore comprises a binary counter with N flip-flops (P1, P2 . . . PN) and operates as follows: the lowest weight of the binary values contained in the flip-flops is the weight of the binary value contained in the flip-flop of position 1 (Pi), while the highest weight of such binary values is the weight of the binary value contained in the flip-flop of position N (P.sub.N); the result is 2.sup.N combinations which are all the possible combinations which exist when the levels 1 and 0 are put on the N flip-flops. On initialisation all the flip-flops of the binary counter are reset through zero. The flip-flops are of course connected to a clock which supplies pulses to them; at the first clock pulse the flip-flop P.sub.1 of position 1 passes to the logic level 1. The changeover of the flip-flop P.sub.1 therefore supplies two counting positions in association with the flip-flop P.sub.2 which is at the logic level 0, all the other flip-flops of the counter being also at the logic level 0. Counting is continued by putting the flip-flop P.sub.2 at the logic level 1 and by starting to sweep again the various possibilities offered by the flip-flop P.sub.1 which can be either at the logic level 0 or at the logic level 1. The flip-flop P.sub.2 therefore supplies two possibilities of choice (logic level 0 or logic level 1) which, associated with the logic level of the flip-flop P.sub.1, gives two fresh possibilities--i.e., a total of 2 ex 2=4 combinations. Thus, step by step, every time all the combinations are swept, the flip-flop of the directly higher weight is set to 1, while all the flip-flops of lower weight are reset to 0. It results from these observations that, as a result of a binary counter whose outputs are swept, it is possible to obtain 2.sup.N combinations.
However, the total number of combinations to be swept is very great when N has a considerable value.